Salary : As Per Industry Standards.
Job Views: 50
Build and maintain a smart and scalable verification environment that ties into various
systems (SW stack, FPGA, and ASIC RTL)
Create IP level module and sub-system verification plan, TB, portable test benches,
sequences, test infrastructure.
Work with the Systems, design, and micro-architecture teams to understand the
functional and performance goals.
Review specifications and develop attributes, tests, and coverage plans.
Work closely with the external verification teams and design houses.
Recruiter: Akanksha Dwivedi- +91 6359655665
Created Date: 12-04-2022
Responsibilities: SENIOR VERIFICATION ENGINEER
We are looking for a talented and experienced engineer to take part in the verification efforts
for the company. This position involves building a complex verification environment from
scratch, and defining and executing a test plan. In this role, you will develop reusable best-in-
class UVM TB, implement effective coverage driven and directed test cases, deploy new tools,
and implement methodologies to improve quality of tape-out readiness.
SENIOR VERIFICATION ENGINEER
Experience Requirements:Key Qualifications 6+ years of verification experience, including dedicated/hands-on experience buildingcomplex environments from scratch for ASIC verification. Proven track record of working full ASIC cycle from concept to tape-out to bring-up. Advanced knowledge of HVL methodology (UVM/OVM) with most recent experience inUVM and industry standard tools, including Verilog, Verilog simulator, and debug. Clear understanding of constrained random verification process, functional coverage,code coverage, and assertion methodology and philosophy Master’s degree in electrical engineering or computer science, or equivalent experience Great teammate with excellent communication and problem-solving skills and thedesire to seek diverse challenges. Experience with Mix-Signal ASIC verification – an advantage
Salary Range: As Per Industry Standards.